mirror of
https://github.com/thelsing/knx.git
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258 lines
9.8 KiB
C
258 lines
9.8 KiB
C
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//*********************************************************************************
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// Generated by SmartRF Studio version 2.6.0 (build #8)
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// Tested for SimpleLink SDK version: CC13x0 SDK 1.30.xx.xx
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// Device: CC1310 Rev. 2.1
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//
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//*********************************************************************************
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//*********************************************************************************
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// Parameter summary
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// Address: on
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// Address0: 0x44FF
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// Frequency: 868.29999 MHz
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// Data Format: Serial mode disable
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// Deviation: 50.000 kHz
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// Max Packet Length: unlimited packet length mode
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// RX Filter BW: 196 kHz
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// Symbol Rate: 32.76825 kBaud
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// Sync Word Length: 24 Bits
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// TX Power: 14 dBm (requires define CCFG_FORCE_VDDR_HH = 1 in ccfg.c, see CC13xx/CC26xx Technical Reference Manual)
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// Whitening: No whitening
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// FEC mode: manchester code
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#include <ti/devices/DeviceFamily.h>
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#include DeviceFamily_constructPath(driverlib/rf_mailbox.h)
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#include DeviceFamily_constructPath(driverlib/rf_common_cmd.h)
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#include DeviceFamily_constructPath(driverlib/rf_prop_cmd.h)
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#include <ti/drivers/rf/RF.h>
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#include DeviceFamily_constructPath(rf_patches/rf_patch_cpe_wmbus_smode.h)
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#include DeviceFamily_constructPath(rf_patches/rf_patch_mce_wmbus_smode.h)
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#include DeviceFamily_constructPath(rf_patches/rf_patch_rfe_wmbus_smode.h)
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#include "smartrf_settings.h"
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// TI-RTOS RF Mode Object
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RF_Mode RF_prop =
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{
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.rfMode = RF_MODE_PROPRIETARY_SUB_1,
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.cpePatchFxn = &rf_patch_cpe_wmbus_smode,
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.mcePatchFxn = &rf_patch_mce_wmbus_smode,
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.rfePatchFxn = &rf_patch_rfe_wmbus_smode,
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};
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// Overrides for CMD_PROP_RADIO_DIV_SETUP
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static uint32_t pOverrides[] =
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{
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// PHY: Run the MCE and RFE patches
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MCE_RFE_OVERRIDE(1,0,0,1,0,0),
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// override_synth_prop_863_930_div5.xml
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// Synth: Set recommended RTRIM to 7
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HW_REG_OVERRIDE(0x4038,0x0037),
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// Synth: Set Fref to 4 MHz
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(uint32_t)0x000684A3,
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// Synth: Configure fine calibration setting
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HW_REG_OVERRIDE(0x4020,0x7F00),
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// Synth: Configure fine calibration setting
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HW_REG_OVERRIDE(0x4064,0x0040),
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// Synth: Configure fine calibration setting
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(uint32_t)0xB1070503,
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// Synth: Configure fine calibration setting
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(uint32_t)0x05330523,
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// Synth: Set loop bandwidth after lock to 20 kHz
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(uint32_t)0x0A480583,
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// Synth: Set loop bandwidth after lock to 20 kHz
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(uint32_t)0x7AB80603,
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// Synth: Configure VCO LDO (in ADI1, set VCOLDOCFG=0x9F to use voltage input reference)
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ADI_REG_OVERRIDE(1,4,0x9F),
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// Synth: Configure synth LDO (in ADI1, set SLDOCTL0.COMP_CAP=1)
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ADI_HALFREG_OVERRIDE(1,7,0x4,0x4),
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// Synth: Use 24 MHz XOSC as synth clock, enable extra PLL filtering
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(uint32_t)0x02010403,
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// Synth: Configure extra PLL filtering
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(uint32_t)0x00108463,
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// Synth: Increase synth programming timeout (0x04B0 RAT ticks = 300 us)
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(uint32_t)0x04B00243,
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// override_synth_disable_bias_div5.xml
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// Synth: Set divider bias to disabled
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HW32_ARRAY_OVERRIDE(0x405C,1),
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// Synth: Set divider bias to disabled (specific for loDivider=5)
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(uint32_t)0x18000200,
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// override_phy_rx_aaf_bw_0xd.xml
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// Rx: Set anti-aliasing filter bandwidth to 0xD (in ADI0, set IFAMPCTL3[7:4]=0xD)
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ADI_HALFREG_OVERRIDE(0,61,0xF,0xD),
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// override_phy_gfsk_rx.xml
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// Rx: Set LNA bias current trim offset to 3
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(uint32_t)0x00038883,
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// Rx: Freeze RSSI on sync found event
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HW_REG_OVERRIDE(0x6084,0x35F1),
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// Tx: Configure PA ramping setting (0x61). Rx: Set AGC reference level to 0x1F
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HW_REG_OVERRIDE(0x6088,0x611F),
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// Tx: Configure PA ramping setting and setting AGC settle wait = 21 samples
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HW_REG_OVERRIDE(0x608C,0x8112),
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// Rx: Set RSSI offset to adjust reported RSSI by +7 dB
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(uint32_t)0x00F988A3,
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// TX power override
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// Tx: Set PA trim to max (in ADI0, set PACTL0=0xF8)
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ADI_REG_OVERRIDE(0,12,0xF8),
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// Set AGC win size = 7 samples
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HW_REG_OVERRIDE(0x6064,0x1306),
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(uint32_t)0xFFFFFFFF,
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};
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// CMD_PROP_RADIO_DIV_SETUP
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rfc_CMD_PROP_RADIO_DIV_SETUP_t RF_cmdPropRadioDivSetup =
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{
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.commandNo = 0x3807,
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.status = 0x0000,
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.pNextOp = 0, // INSERT APPLICABLE POINTER: (uint8_t*)&xxx
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.startTime = 0x00000000,
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.startTrigger.triggerType = 0x0,
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.startTrigger.bEnaCmd = 0x0,
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.startTrigger.triggerNo = 0x0,
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.startTrigger.pastTrig = 0x0,
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.condition.rule = 0x1,
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.condition.nSkip = 0x0,
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.modulation.modType = 0x0,
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.modulation.deviation = 0xC8,
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.symbolRate.preScale = 0xF,
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.symbolRate.rateWord = 0x53E3,
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.rxBw = 0x27, // S2-mode (for S1-mode, rxBw = 0x29)
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.preamConf.nPreamBytes = 0x3,
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.preamConf.preamMode = 0x0,
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.formatConf.nSwBits = 0x18,
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.formatConf.bBitReversal = 0x0,
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.formatConf.bMsbFirst = 0x1,
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.formatConf.fecMode = 0x0a, // manchester coding
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.formatConf.whitenMode = 0x0,
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.config.frontEndMode = 0x0,
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.config.biasMode = 0x1,
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.config.analogCfgMode = 0x0,
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.config.bNoFsPowerUp = 0x0,
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.txPower = 0xA73F,
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.pRegOverride = pOverrides,
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.centerFreq = 0x0364,
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.intFreq = 0x8000,
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.loDivider = 0x05,
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};
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// CMD_FS
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rfc_CMD_FS_t RF_cmdFs =
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{
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.commandNo = 0x0803,
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.status = 0x0000,
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.pNextOp = 0, // INSERT APPLICABLE POINTER: (uint8_t*)&xxx
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.startTime = 0x00000000,
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.startTrigger.triggerType = 0x0,
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.startTrigger.bEnaCmd = 0x0,
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.startTrigger.triggerNo = 0x0,
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.startTrigger.pastTrig = 0x0,
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.condition.rule = 0x1,
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.condition.nSkip = 0x0,
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.frequency = 0x0364,
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.fractFreq = 0x4CCD,
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.synthConf.bTxMode = 0x0,
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.synthConf.refFreq = 0x0,
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.__dummy0 = 0x00,
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.__dummy1 = 0x00,
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.__dummy2 = 0x00,
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.__dummy3 = 0x0000,
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};
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// CMD_PROP_TX
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rfc_CMD_PROP_TX_t RF_cmdPropTx =
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{
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.commandNo = 0x3801,
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.status = 0x0000,
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.pNextOp = 0, // INSERT APPLICABLE POINTER: (uint8_t*)&xxx
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.startTime = 0x00000000,
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.startTrigger.triggerType = 0x0,
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.startTrigger.bEnaCmd = 0x0,
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.startTrigger.triggerNo = 0x0,
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.startTrigger.pastTrig = 0x0,
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.condition.rule = 0x1,
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.condition.nSkip = 0x0,
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.pktConf.bFsOff = 0x0, // 0: Keep synthesizer running after end trigger
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.pktConf.bUseCrc = 0x0, // CRC engine cannot be used
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.pktConf.bVarLen = 0x0, // 0: Fixed length
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.pktLen = 0x00, // SET APPLICATION PAYLOAD LENGTH
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.syncWord = 0x547696,
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.pPkt = 0, // INSERT APPLICABLE POINTER: (uint8_t*)&xxx
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};
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// CMD_PROP_RX_ADV
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rfc_CMD_PROP_RX_ADV_t RF_cmdPropRxAdv =
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{
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.commandNo = 0x3804,
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.status = 0x0000,
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.pNextOp = 0, // INSERT APPLICABLE POINTER: (uint8_t*)&xxx
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.startTime = 0x00000000,
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.startTrigger.triggerType = 0x0,
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.startTrigger.bEnaCmd = 0x0,
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.startTrigger.triggerNo = 0x0,
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.startTrigger.pastTrig = 0x0,
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.condition.rule = 0x1,
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.condition.nSkip = 0x0,
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.pktConf.bFsOff = 0x0, // 0: Keep synthesizer running after end trigger
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.pktConf.bRepeatOk = 0x0,
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.pktConf.bRepeatNok = 0x0,
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.pktConf.bUseCrc = 0x0, // CRC engine cannot be used
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.pktConf.bCrcIncSw = 0x0,
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.pktConf.bCrcIncHdr = 0x1,
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.pktConf.endType = 0x0,
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.pktConf.filterOp = 0x0, // 0: Abort packet reception and restart syncword search
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.rxConf.bAutoFlushIgnored = 0x0, // Not supported for partial RX buffers
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.rxConf.bAutoFlushCrcErr = 0x0,
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.rxConf.bIncludeHdr = 0x1,
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.rxConf.bIncludeCrc = 0x0,
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.rxConf.bAppendRssi = 0x0,
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.rxConf.bAppendTimestamp = 0x0,
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.rxConf.bAppendStatus = 0x0,
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.syncWord0 = 0x547696, // KNX-RF syncword
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.syncWord1 = 0,
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.maxPktLen = 0,
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.hdrConf.numHdrBits = 8, // One length byte in header
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.hdrConf.lenPos = 0,
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.hdrConf.numLenBits = 0, // Engine shall not read the length itself. We set it later. (maxPktLen must be 0!)
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.addrConf.addrType = 0, // Address bytes AFTER header
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.addrConf.addrSize = 2, // use the two fixed bytes (0x44 and 0xff) after the length byte as address bytes
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.addrConf.addrPos = 0,
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.addrConf.numAddr = 1, // just the two fixed bytes are used as one address
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.lenOffset = 0,
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.endTrigger.triggerType = 0x1,
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.endTrigger.bEnaCmd = 0x0,
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.endTrigger.triggerNo = 0x0,
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.endTrigger.pastTrig = 0x0,
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.endTime = 0x00000000,
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.pAddr = 0, // INSERT APPLICABLE POINTER: (uint8_t*)&xxx
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.pQueue = 0, // INSERT APPLICABLE POINTER: (dataQueue_t*)&xxx
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.pOutput = 0, // INSERT APPLICABLE POINTER: (uint8_t*)&xxx
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};
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// TX Power table
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// The RF_TxPowerTable_DEFAULT_PA_ENTRY macro is defined in RF.h and requires the following arguments:
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// RF_TxPowerTable_DEFAULT_PA_ENTRY(bias, gain, boost coefficient)
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// See the Technical Reference Manual for further details about the "txPower" Command field.
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// The PA settings require the CCFG_FORCE_VDDR_HH = 0 unless stated otherwise.
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const RF_TxPowerTable_Entry PROP_RF_txPowerTable[] =
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{
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{-10, RF_TxPowerTable_DEFAULT_PA_ENTRY(0, 3, 0, 4) },
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{0, RF_TxPowerTable_DEFAULT_PA_ENTRY(1, 1, 0, 0) },
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{1, RF_TxPowerTable_DEFAULT_PA_ENTRY(3, 3, 0, 8) },
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{2, RF_TxPowerTable_DEFAULT_PA_ENTRY(2, 1, 0, 8) },
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{3, RF_TxPowerTable_DEFAULT_PA_ENTRY(4, 3, 0, 10) },
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{4, RF_TxPowerTable_DEFAULT_PA_ENTRY(5, 3, 0, 12) },
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{5, RF_TxPowerTable_DEFAULT_PA_ENTRY(6, 3, 0, 12) },
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{6, RF_TxPowerTable_DEFAULT_PA_ENTRY(7, 3, 0, 14) },
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{7, RF_TxPowerTable_DEFAULT_PA_ENTRY(9, 3, 0, 16) },
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{8, RF_TxPowerTable_DEFAULT_PA_ENTRY(11, 3, 0, 18) },
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{9, RF_TxPowerTable_DEFAULT_PA_ENTRY(13, 3, 0, 22) },
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{10, RF_TxPowerTable_DEFAULT_PA_ENTRY(19, 3, 0, 28) },
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{11, RF_TxPowerTable_DEFAULT_PA_ENTRY(26, 3, 0, 40) },
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{12, RF_TxPowerTable_DEFAULT_PA_ENTRY(24, 0, 0, 92) },
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{13, RF_TxPowerTable_DEFAULT_PA_ENTRY(63, 0, 0, 83) }, // The original PA value (12.5 dBm) have been rounded to an integer value.
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{14, RF_TxPowerTable_DEFAULT_PA_ENTRY(63, 0, 1, 83) }, // This setting requires CCFG_FORCE_VDDR_HH = 1.
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RF_TxPowerTable_TERMINATION_ENTRY
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};
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const uint8_t PROP_RF_txPowerTableSize = sizeof(PROP_RF_txPowerTable)/sizeof(RF_TxPowerTable_Entry);
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