mirror of
https://github.com/thelsing/knx.git
synced 2025-10-26 10:26:25 +01:00
d90843ba45
* Initial commit * Clean up * Remove display code * Change cmake build * Add SimpleLink SDK for CC13xx/CC26xx as submodule * Remove commented line from build.sh * Working build * Remove SDK submodule * Squashed 'examples/knx-cc1310/coresdk_cc13xx_cc26xx/' content from commit 0d78d32 git-subtree-dir: examples/knx-cc1310/coresdk_cc13xx_cc26xx git-subtree-split: 0d78d3280357416a5c0388148cda13717c9ffaa5 * Add more comments and enable Power_idleFunc() for NoRTOS variant. Internal SDK driver functions which have to wait for something will cause Power_idleFunc to be called instead of doing busy wait. * Move CC1310 platform init around * Optimize a bit more in debug build config as the binary does not fit into 128Kb flash otherwise. * Explicitly list each source/header file in build config. Use linker group to resolve circular dependencies. * Ignore vscode settings.json * Increase stacks size * Only compile CC1310 source code if #define DeviceFamily_CC13X0 * initial commit of CC1310 RF driver with first working RX version * Better handling of buttonUp() across platforms * Start cleanup * continue cleanup * Fix bau2920 compilation * Continue cleanup * Fix compilation in other examples * Fix compilation * htons() and ntohs() only for SAMD and STM32, but not for Linux and ESP8266 and ESP32 * htons(9 and ntohs() needed for CC13x0 * Continue cleanup * Add CC1310 platform to CI * Fix CI * Use more recent toolchain from ARM * Fix travis * Use Ubuntu Focal * Fix toolchain for travis * Fix package name * Fix toolchain * Add libstdc++-dev package * Add newlib packages * Remove commented commands from CI * Fix travis * Fix compilation of knxPython * Clean up linefeeds * Fix RX callback * Move RF CRC16-DNP to bits.cpp * Fix TX * Optimization: do not calc CRC for block1 again in rf_data_link_layer * Make newline optional in printHex * Cleanup. First working version: ETS5 programming of individual address via KNX/RF coupler. * Use LEDs and Buttons to control ProgMode and Flash Erase * Remove settings.json (VScode) * Add README.md * Update README.md * Update README.md * Fix typo
258 lines
9.8 KiB
C
258 lines
9.8 KiB
C
//*********************************************************************************
|
|
// Generated by SmartRF Studio version 2.6.0 (build #8)
|
|
// Tested for SimpleLink SDK version: CC13x0 SDK 1.30.xx.xx
|
|
// Device: CC1310 Rev. 2.1
|
|
//
|
|
//*********************************************************************************
|
|
|
|
//*********************************************************************************
|
|
// Parameter summary
|
|
// Address: on
|
|
// Address0: 0x44FF
|
|
// Frequency: 868.29999 MHz
|
|
// Data Format: Serial mode disable
|
|
// Deviation: 50.000 kHz
|
|
// Max Packet Length: unlimited packet length mode
|
|
// RX Filter BW: 196 kHz
|
|
// Symbol Rate: 32.76825 kBaud
|
|
// Sync Word Length: 24 Bits
|
|
// TX Power: 14 dBm (requires define CCFG_FORCE_VDDR_HH = 1 in ccfg.c, see CC13xx/CC26xx Technical Reference Manual)
|
|
// Whitening: No whitening
|
|
// FEC mode: manchester code
|
|
|
|
#include <ti/devices/DeviceFamily.h>
|
|
#include DeviceFamily_constructPath(driverlib/rf_mailbox.h)
|
|
#include DeviceFamily_constructPath(driverlib/rf_common_cmd.h)
|
|
#include DeviceFamily_constructPath(driverlib/rf_prop_cmd.h)
|
|
#include <ti/drivers/rf/RF.h>
|
|
#include DeviceFamily_constructPath(rf_patches/rf_patch_cpe_wmbus_smode.h)
|
|
#include DeviceFamily_constructPath(rf_patches/rf_patch_mce_wmbus_smode.h)
|
|
#include DeviceFamily_constructPath(rf_patches/rf_patch_rfe_wmbus_smode.h)
|
|
#include "smartrf_settings.h"
|
|
|
|
|
|
// TI-RTOS RF Mode Object
|
|
RF_Mode RF_prop =
|
|
{
|
|
.rfMode = RF_MODE_PROPRIETARY_SUB_1,
|
|
.cpePatchFxn = &rf_patch_cpe_wmbus_smode,
|
|
.mcePatchFxn = &rf_patch_mce_wmbus_smode,
|
|
.rfePatchFxn = &rf_patch_rfe_wmbus_smode,
|
|
};
|
|
|
|
// Overrides for CMD_PROP_RADIO_DIV_SETUP
|
|
static uint32_t pOverrides[] =
|
|
{
|
|
// PHY: Run the MCE and RFE patches
|
|
MCE_RFE_OVERRIDE(1,0,0,1,0,0),
|
|
// override_synth_prop_863_930_div5.xml
|
|
// Synth: Set recommended RTRIM to 7
|
|
HW_REG_OVERRIDE(0x4038,0x0037),
|
|
// Synth: Set Fref to 4 MHz
|
|
(uint32_t)0x000684A3,
|
|
// Synth: Configure fine calibration setting
|
|
HW_REG_OVERRIDE(0x4020,0x7F00),
|
|
// Synth: Configure fine calibration setting
|
|
HW_REG_OVERRIDE(0x4064,0x0040),
|
|
// Synth: Configure fine calibration setting
|
|
(uint32_t)0xB1070503,
|
|
// Synth: Configure fine calibration setting
|
|
(uint32_t)0x05330523,
|
|
// Synth: Set loop bandwidth after lock to 20 kHz
|
|
(uint32_t)0x0A480583,
|
|
// Synth: Set loop bandwidth after lock to 20 kHz
|
|
(uint32_t)0x7AB80603,
|
|
// Synth: Configure VCO LDO (in ADI1, set VCOLDOCFG=0x9F to use voltage input reference)
|
|
ADI_REG_OVERRIDE(1,4,0x9F),
|
|
// Synth: Configure synth LDO (in ADI1, set SLDOCTL0.COMP_CAP=1)
|
|
ADI_HALFREG_OVERRIDE(1,7,0x4,0x4),
|
|
// Synth: Use 24 MHz XOSC as synth clock, enable extra PLL filtering
|
|
(uint32_t)0x02010403,
|
|
// Synth: Configure extra PLL filtering
|
|
(uint32_t)0x00108463,
|
|
// Synth: Increase synth programming timeout (0x04B0 RAT ticks = 300 us)
|
|
(uint32_t)0x04B00243,
|
|
// override_synth_disable_bias_div5.xml
|
|
// Synth: Set divider bias to disabled
|
|
HW32_ARRAY_OVERRIDE(0x405C,1),
|
|
// Synth: Set divider bias to disabled (specific for loDivider=5)
|
|
(uint32_t)0x18000200,
|
|
// override_phy_rx_aaf_bw_0xd.xml
|
|
// Rx: Set anti-aliasing filter bandwidth to 0xD (in ADI0, set IFAMPCTL3[7:4]=0xD)
|
|
ADI_HALFREG_OVERRIDE(0,61,0xF,0xD),
|
|
// override_phy_gfsk_rx.xml
|
|
// Rx: Set LNA bias current trim offset to 3
|
|
(uint32_t)0x00038883,
|
|
// Rx: Freeze RSSI on sync found event
|
|
HW_REG_OVERRIDE(0x6084,0x35F1),
|
|
// Tx: Configure PA ramping setting (0x61). Rx: Set AGC reference level to 0x1F
|
|
HW_REG_OVERRIDE(0x6088,0x611F),
|
|
// Tx: Configure PA ramping setting and setting AGC settle wait = 21 samples
|
|
HW_REG_OVERRIDE(0x608C,0x8112),
|
|
// Rx: Set RSSI offset to adjust reported RSSI by +7 dB
|
|
(uint32_t)0x00F988A3,
|
|
// TX power override
|
|
// Tx: Set PA trim to max (in ADI0, set PACTL0=0xF8)
|
|
ADI_REG_OVERRIDE(0,12,0xF8),
|
|
// Set AGC win size = 7 samples
|
|
HW_REG_OVERRIDE(0x6064,0x1306),
|
|
(uint32_t)0xFFFFFFFF,
|
|
};
|
|
|
|
// CMD_PROP_RADIO_DIV_SETUP
|
|
rfc_CMD_PROP_RADIO_DIV_SETUP_t RF_cmdPropRadioDivSetup =
|
|
{
|
|
.commandNo = 0x3807,
|
|
.status = 0x0000,
|
|
.pNextOp = 0, // INSERT APPLICABLE POINTER: (uint8_t*)&xxx
|
|
.startTime = 0x00000000,
|
|
.startTrigger.triggerType = 0x0,
|
|
.startTrigger.bEnaCmd = 0x0,
|
|
.startTrigger.triggerNo = 0x0,
|
|
.startTrigger.pastTrig = 0x0,
|
|
.condition.rule = 0x1,
|
|
.condition.nSkip = 0x0,
|
|
.modulation.modType = 0x0,
|
|
.modulation.deviation = 0xC8,
|
|
.symbolRate.preScale = 0xF,
|
|
.symbolRate.rateWord = 0x53E3,
|
|
.rxBw = 0x27, // S2-mode (for S1-mode, rxBw = 0x29)
|
|
.preamConf.nPreamBytes = 0x3,
|
|
.preamConf.preamMode = 0x0,
|
|
.formatConf.nSwBits = 0x18,
|
|
.formatConf.bBitReversal = 0x0,
|
|
.formatConf.bMsbFirst = 0x1,
|
|
.formatConf.fecMode = 0x0a, // manchester coding
|
|
.formatConf.whitenMode = 0x0,
|
|
.config.frontEndMode = 0x0,
|
|
.config.biasMode = 0x1,
|
|
.config.analogCfgMode = 0x0,
|
|
.config.bNoFsPowerUp = 0x0,
|
|
.txPower = 0xA73F,
|
|
.pRegOverride = pOverrides,
|
|
.centerFreq = 0x0364,
|
|
.intFreq = 0x8000,
|
|
.loDivider = 0x05,
|
|
};
|
|
|
|
// CMD_FS
|
|
rfc_CMD_FS_t RF_cmdFs =
|
|
{
|
|
.commandNo = 0x0803,
|
|
.status = 0x0000,
|
|
.pNextOp = 0, // INSERT APPLICABLE POINTER: (uint8_t*)&xxx
|
|
.startTime = 0x00000000,
|
|
.startTrigger.triggerType = 0x0,
|
|
.startTrigger.bEnaCmd = 0x0,
|
|
.startTrigger.triggerNo = 0x0,
|
|
.startTrigger.pastTrig = 0x0,
|
|
.condition.rule = 0x1,
|
|
.condition.nSkip = 0x0,
|
|
.frequency = 0x0364,
|
|
.fractFreq = 0x4CCD,
|
|
.synthConf.bTxMode = 0x0,
|
|
.synthConf.refFreq = 0x0,
|
|
.__dummy0 = 0x00,
|
|
.__dummy1 = 0x00,
|
|
.__dummy2 = 0x00,
|
|
.__dummy3 = 0x0000,
|
|
};
|
|
|
|
// CMD_PROP_TX
|
|
rfc_CMD_PROP_TX_t RF_cmdPropTx =
|
|
{
|
|
.commandNo = 0x3801,
|
|
.status = 0x0000,
|
|
.pNextOp = 0, // INSERT APPLICABLE POINTER: (uint8_t*)&xxx
|
|
.startTime = 0x00000000,
|
|
.startTrigger.triggerType = 0x0,
|
|
.startTrigger.bEnaCmd = 0x0,
|
|
.startTrigger.triggerNo = 0x0,
|
|
.startTrigger.pastTrig = 0x0,
|
|
.condition.rule = 0x1,
|
|
.condition.nSkip = 0x0,
|
|
.pktConf.bFsOff = 0x0, // 0: Keep synthesizer running after end trigger
|
|
.pktConf.bUseCrc = 0x0, // CRC engine cannot be used
|
|
.pktConf.bVarLen = 0x0, // 0: Fixed length
|
|
.pktLen = 0x00, // SET APPLICATION PAYLOAD LENGTH
|
|
.syncWord = 0x547696,
|
|
.pPkt = 0, // INSERT APPLICABLE POINTER: (uint8_t*)&xxx
|
|
};
|
|
|
|
// CMD_PROP_RX_ADV
|
|
rfc_CMD_PROP_RX_ADV_t RF_cmdPropRxAdv =
|
|
{
|
|
.commandNo = 0x3804,
|
|
.status = 0x0000,
|
|
.pNextOp = 0, // INSERT APPLICABLE POINTER: (uint8_t*)&xxx
|
|
.startTime = 0x00000000,
|
|
.startTrigger.triggerType = 0x0,
|
|
.startTrigger.bEnaCmd = 0x0,
|
|
.startTrigger.triggerNo = 0x0,
|
|
.startTrigger.pastTrig = 0x0,
|
|
.condition.rule = 0x1,
|
|
.condition.nSkip = 0x0,
|
|
.pktConf.bFsOff = 0x0, // 0: Keep synthesizer running after end trigger
|
|
.pktConf.bRepeatOk = 0x0,
|
|
.pktConf.bRepeatNok = 0x0,
|
|
.pktConf.bUseCrc = 0x0, // CRC engine cannot be used
|
|
.pktConf.bCrcIncSw = 0x0,
|
|
.pktConf.bCrcIncHdr = 0x1,
|
|
.pktConf.endType = 0x0,
|
|
.pktConf.filterOp = 0x0, // 0: Abort packet reception and restart syncword search
|
|
.rxConf.bAutoFlushIgnored = 0x0, // Not supported for partial RX buffers
|
|
.rxConf.bAutoFlushCrcErr = 0x0,
|
|
.rxConf.bIncludeHdr = 0x1,
|
|
.rxConf.bIncludeCrc = 0x0,
|
|
.rxConf.bAppendRssi = 0x0,
|
|
.rxConf.bAppendTimestamp = 0x0,
|
|
.rxConf.bAppendStatus = 0x0,
|
|
.syncWord0 = 0x547696, // KNX-RF syncword
|
|
.syncWord1 = 0,
|
|
.maxPktLen = 0,
|
|
.hdrConf.numHdrBits = 8, // One length byte in header
|
|
.hdrConf.lenPos = 0,
|
|
.hdrConf.numLenBits = 0, // Engine shall not read the length itself. We set it later. (maxPktLen must be 0!)
|
|
.addrConf.addrType = 0, // Address bytes AFTER header
|
|
.addrConf.addrSize = 2, // use the two fixed bytes (0x44 and 0xff) after the length byte as address bytes
|
|
.addrConf.addrPos = 0,
|
|
.addrConf.numAddr = 1, // just the two fixed bytes are used as one address
|
|
.lenOffset = 0,
|
|
.endTrigger.triggerType = 0x1,
|
|
.endTrigger.bEnaCmd = 0x0,
|
|
.endTrigger.triggerNo = 0x0,
|
|
.endTrigger.pastTrig = 0x0,
|
|
.endTime = 0x00000000,
|
|
.pAddr = 0, // INSERT APPLICABLE POINTER: (uint8_t*)&xxx
|
|
.pQueue = 0, // INSERT APPLICABLE POINTER: (dataQueue_t*)&xxx
|
|
.pOutput = 0, // INSERT APPLICABLE POINTER: (uint8_t*)&xxx
|
|
};
|
|
|
|
// TX Power table
|
|
// The RF_TxPowerTable_DEFAULT_PA_ENTRY macro is defined in RF.h and requires the following arguments:
|
|
// RF_TxPowerTable_DEFAULT_PA_ENTRY(bias, gain, boost coefficient)
|
|
// See the Technical Reference Manual for further details about the "txPower" Command field.
|
|
// The PA settings require the CCFG_FORCE_VDDR_HH = 0 unless stated otherwise.
|
|
const RF_TxPowerTable_Entry PROP_RF_txPowerTable[] =
|
|
{
|
|
{-10, RF_TxPowerTable_DEFAULT_PA_ENTRY(0, 3, 0, 4) },
|
|
{0, RF_TxPowerTable_DEFAULT_PA_ENTRY(1, 1, 0, 0) },
|
|
{1, RF_TxPowerTable_DEFAULT_PA_ENTRY(3, 3, 0, 8) },
|
|
{2, RF_TxPowerTable_DEFAULT_PA_ENTRY(2, 1, 0, 8) },
|
|
{3, RF_TxPowerTable_DEFAULT_PA_ENTRY(4, 3, 0, 10) },
|
|
{4, RF_TxPowerTable_DEFAULT_PA_ENTRY(5, 3, 0, 12) },
|
|
{5, RF_TxPowerTable_DEFAULT_PA_ENTRY(6, 3, 0, 12) },
|
|
{6, RF_TxPowerTable_DEFAULT_PA_ENTRY(7, 3, 0, 14) },
|
|
{7, RF_TxPowerTable_DEFAULT_PA_ENTRY(9, 3, 0, 16) },
|
|
{8, RF_TxPowerTable_DEFAULT_PA_ENTRY(11, 3, 0, 18) },
|
|
{9, RF_TxPowerTable_DEFAULT_PA_ENTRY(13, 3, 0, 22) },
|
|
{10, RF_TxPowerTable_DEFAULT_PA_ENTRY(19, 3, 0, 28) },
|
|
{11, RF_TxPowerTable_DEFAULT_PA_ENTRY(26, 3, 0, 40) },
|
|
{12, RF_TxPowerTable_DEFAULT_PA_ENTRY(24, 0, 0, 92) },
|
|
{13, RF_TxPowerTable_DEFAULT_PA_ENTRY(63, 0, 0, 83) }, // The original PA value (12.5 dBm) have been rounded to an integer value.
|
|
{14, RF_TxPowerTable_DEFAULT_PA_ENTRY(63, 0, 1, 83) }, // This setting requires CCFG_FORCE_VDDR_HH = 1.
|
|
RF_TxPowerTable_TERMINATION_ENTRY
|
|
};
|
|
|
|
const uint8_t PROP_RF_txPowerTableSize = sizeof(PROP_RF_txPowerTable)/sizeof(RF_TxPowerTable_Entry);
|