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439 lines
15 KiB
C
439 lines
15 KiB
C
/*
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* Copyright (c) 2015-2018, Texas Instruments Incorporated
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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*
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* * Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
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* THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
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* PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
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* CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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* EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
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* PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS;
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* OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY,
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* WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
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* OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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* EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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/** ============================================================================
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* @file UDMACC26XX.h
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*
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* @brief UDMACC26XX driver implementation.
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*
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* # Driver include #
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* The UDMACC26XX header file should be included in an application as follows:
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* @code
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* #include <ti/drivers/dma/UDMACC26XX.h>
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* @endcode
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*
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* # Overview #
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* The UDMACC26XX driver currently only supports being used by the SPICC26XXDMA.h. module.
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* In other words, the application should never call any of the functions in this file.
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*
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* # General Behavior #
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* This driver is used implicitly by the SPICC26XXDMA.h driver so user should not
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* have to interface to this driver from the application.
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* The uDMA HW makes use of a control table in RAM which must be 1024 bytes aligned.
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* The default base address of this control table is 0x20000400, however this
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* can be changed by simply changing UDMACC26XX_CONFIG_BASE.
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* The SPICC26XXDMA.h supports SPI0 and SPI1, and uses both TX and RX DMA channels.
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* Each control table entry is 16 bytes, so if an application uses both SSI0 and SSI1
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* the total RAM usage will be 4*16=64 bytes. If only one SSI module is used
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* only 2*16=32 bytes of RAM is used. Please see [Use cases] (@ref USE_CASE) for example.
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*
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* # Error handling #
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* Error handling is handled by the overlying driver which uses the DMA, currently
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* this is only SPICC26XXDMA.h
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*
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* # Power management #
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* Power management is handled by the overlying driver which uses the DMA, currently
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* this is only SPICC26XXDMA.h
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*
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* # Supported functions #
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* Note that these functions should never be called from the application, they
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* are only called from other drivers. They are however included here for completeness:
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*
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* | API function | Description |
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* |------------------------- |----------------------------------------------------------------|
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* | UDMACC26XX_open() | Initialize and enable the uDMA HW and set system dependencies. |
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* | UDMACC26XX_close() | Disable uUDMA HW and release system dependencies |
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*
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* @note These functions should not be called by code. These functions are called
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* by drivers who're using the DMA.
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*
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* # Unsupported Functionality #
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* No known limitations
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*
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* # Use Cases @anchor USE_CASE #
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* The DMA is only used together with the SPICC26XXDMA.h driver, so the application
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* should never call any of the functions in this driver directly.
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* The only thing that the application is allowed to modify is the base address
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* of the DMA control table in RAM. (Default value is 0x2000_0400)
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* Remember it must be 1024 bytes aligned.
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* @code
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* #define UDMACC26XX_CONFIG_BASE 0x2000_0400
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* @endcode
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*
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* - If only SSI0 is used, this will allocate 2*16=32 RAM bytes at address:\n
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* [0x2000_0430-0x2000_044F] = SSI0 RX/TX DMA channels
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* - If only SSI1 is used, this will allocate 2*16=32 RAM bytes at address:\n
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* [0x2000_0500-0x2000_051F] = SSI1 RX/TX DMA channels
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* - If both SSI0 and SSI1 are used, this will allocate 4*16=64 RAM bytes at addresses:\n
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* [0x2000_0430-0x2000_044F] = SSI0 RX/TX DMA channels\n
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* [0x2000_0500-0x2000_051F] = SSI1 RX/TX DMA channels
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*
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* # Instrumentation #
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* The SPI driver interface produces log statements if instrumentation is
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* enabled.
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*
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* Diagnostics Mask | Log details |
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* ---------------- | ----------- |
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* Diags_USER1 | basic SPI operations performed |
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* Diags_USER2 | detailed SPI operations performed |
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*
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* ============================================================================
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*/
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#ifndef ti_drivers_UDMACC26XX__include
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#define ti_drivers_UDMACC26XX__include
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#ifdef __cplusplus
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extern "C" {
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#endif
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#include <stdint.h>
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#include <stdbool.h>
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#include <ti/drivers/Power.h>
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#include <ti/drivers/power/PowerCC26XX.h>
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#include <ti/devices/DeviceFamily.h>
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#include DeviceFamily_constructPath(inc/hw_types.h)
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#include DeviceFamily_constructPath(driverlib/udma.h)
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/**
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* @addtogroup DMA_STATUS
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* UDMACC26XX_STATUS_* macros are command codes only defined in the
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* UDMACC26XX.h driver implementation and need to:
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* @code
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* #include <ti/drivers/dma/UDMACC26XX.h>
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* @endcode
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* @{
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*/
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/* Add DMACC26XX_STATUS_* macros here */
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/** @}*/
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/**
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* @addtogroup DMA_CMD
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* UDMACC26XX_CMD_* macros are command codes only defined in the
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* UDMACC26XX.h driver implementation and need to:
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* @code
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* #include <ti/drivers/dma/UDMACC26XX.h>
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* @endcode
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* @{
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*/
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/* Add DMACC26XX_CMD_* macros here */
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/** @}*/
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/*! Base address for the DMA control table, must be 1024 bytes aligned */
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#if !defined(UDMACC26XX_CONFIG_BASE) && (DeviceFamily_PARENT == DeviceFamily_PARENT_CC13X2_CC26X2)
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#define UDMACC26XX_CONFIG_BASE 0x20001800
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#elif !defined(UDMACC26XX_CONFIG_BASE)
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#define UDMACC26XX_CONFIG_BASE 0x20000400
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#endif
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/*! Make sure DMA control table base address is 1024 bytes aligned */
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#if(UDMACC26XX_CONFIG_BASE & 0x3FF)
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#error "Base address for DMA control table 'UDMACC26XX_CONFIG_BASE' must be 1024 bytes aligned."
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#endif
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/*! Compiler specific macros to allocate DMA control table entries */
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#if defined(__IAR_SYSTEMS_ICC__)
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#define ALLOCATE_CONTROL_TABLE_ENTRY(ENTRY_NAME, CHANNEL_INDEX) \
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__no_init static volatile tDMAControlTable ENTRY_NAME @ UDMACC26XX_CONFIG_BASE + CHANNEL_INDEX * sizeof(tDMAControlTable)
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#elif defined(__TI_COMPILER_VERSION__)
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#define ALLOCATE_CONTROL_TABLE_ENTRY(ENTRY_NAME, CHANNEL_INDEX) \
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PRAGMA(LOCATION( ENTRY_NAME , UDMACC26XX_CONFIG_BASE + CHANNEL_INDEX * sizeof(tDMAControlTable) );)\
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static volatile tDMAControlTable ENTRY_NAME
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#define PRAGMA(x) _Pragma(#x)
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#elif defined(__GNUC__)
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#define ALLOCATE_CONTROL_TABLE_ENTRY(ENTRY_NAME, CHANNEL_INDEX) \
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extern int UDMACC26XX_ ## ENTRY_NAME ## _is_placed; __attribute__ ((section("."#ENTRY_NAME))) static volatile tDMAControlTable ENTRY_NAME = {&UDMACC26XX_ ## ENTRY_NAME ## _is_placed}
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#else
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#error "don't know how to define ALLOCATE_CONTROL_TABLE_ENTRY for this toolchain"
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#endif
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/*! Sets the DMA transfer size in number of items */
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#define UDMACC26XX_SET_TRANSFER_SIZE(SIZE) (((SIZE - 1) << UDMA_XFER_SIZE_S) & UDMA_XFER_SIZE_M)
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/*! Gets the DMA transfer size in number of items*/
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#define UDMACC26XX_GET_TRANSFER_SIZE(CONTROL) (((CONTROL & UDMA_XFER_SIZE_M) >> UDMA_XFER_SIZE_S) + 1)
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/*!
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* @brief UDMACC26XX object
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*/
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typedef struct UDMACC26XX_Object {
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bool isOpen; /*!< Flag for open/close status */
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HwiP_Struct hwi; /*!< Embedded Hwi Object */
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} UDMACC26XX_Object;
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/*!
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* @brief UDMACC26XX hardware attributes
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*/
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typedef struct UDMACC26XX_HWAttrs {
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uint32_t baseAddr; /*!< Base adddress for UDMACC26XX */
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PowerCC26XX_Resource powerMngrId; /*!< UDMACC26XX Peripheral's power manager ID */
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uint8_t intNum; /*!< UDMACC26XX error interrupt number */
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/*! @brief UDMACC26XX error interrupt priority.
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* intPriority is the DMA peripheral's interrupt priority, as
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* defined by the underlying OS. It is passed unmodified to the
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* underlying OS's interrupt handler creation code, so you need to
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* refer to the OS documentation for usage. If the
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* driver uses the ti.dpl interface instead of making OS
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* calls directly, then the HwiP port handles the interrupt priority
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* in an OS specific way. In the case of the SYS/BIOS port,
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* intPriority is passed unmodified to Hwi_create().
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*
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* The CC26xx uses three of the priority bits,
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* meaning ~0 has the same effect as (7 << 5).
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*
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* (7 << 5) will apply the lowest priority.
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*
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* (1 << 5) will apply the highest priority.
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*
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* Setting the priority to 0 is not supported by this driver.
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*
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* HWI's with priority 0 ignore the HWI dispatcher to support zero-latency interrupts, thus invalidating the critical sections in this driver.
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*/
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uint8_t intPriority;
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} UDMACC26XX_HWAttrs;
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/*!
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* @brief UDMACC26XX Global configuration
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*/
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typedef struct UDMACC26XX_Config {
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void *object; /*!< Pointer to UDMACC26XX object */
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void const *hwAttrs; /*!< Pointer to hardware attribute */
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} UDMACC26XX_Config;
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/*!
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* @brief A handle that is returned from a UDMACC26XX_open() call.
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*/
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typedef struct UDMACC26XX_Config *UDMACC26XX_Handle;
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/* Extern'd hwiIntFxn */
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extern void UDMACC26XX_hwiIntFxn(uintptr_t callbacks);
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/*!
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* @brief Function to initialize the CC26XX DMA driver
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*
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* The function will set the isOpen flag to false, and should be called prior
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* to opening the DMA driver.
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*
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* @pre Calling context: Hwi, Swi, Task
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*
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* @return none
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*
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* @sa UDMACC26XX_open()
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*/
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__STATIC_INLINE void UDMACC26XX_init(UDMACC26XX_Handle handle)
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{
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UDMACC26XX_Object *object;
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/* Get the pointer to the object */
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object = (UDMACC26XX_Object *)(handle->object);
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/* mark the module as available */
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object->isOpen = false;
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}
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/*!
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* @brief Function to initialize the CC26XX DMA peripheral
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*
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* The function will set a dependency on the peripheral power domain, i.e. power up the
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* module and enable the clock.
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* Note this function always uses the first DMA entry in the global UDMACC26XX_config list.
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*
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* @pre UDMACC26XX_init() has to be called first.
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* Calling context: Task
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*
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* @return UDMACC26XX_Handle on success or NULL if error or if it has been
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* already opened
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*
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* @sa UDMACC26XX_close()
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*/
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extern UDMACC26XX_Handle UDMACC26XX_open();
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/*!
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* @internal
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* @brief Function to enable a given DMA channel
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*
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* @pre UDMACC26XX_open() has to be called first.
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* Calling context: Hwi, Swi, Task
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*
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* @param handle A SPI_Handle returned from SPI_open()
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*
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* @param params A 32-bit bitmask of the channels to enable.
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*
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* @sa UDMACC26XX_channelDisable
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*/
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__STATIC_INLINE void UDMACC26XX_channelEnable(UDMACC26XX_Handle handle, uint32_t channelBitMask)
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{
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UDMACC26XX_HWAttrs const *hwAttrs;
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/* Get the pointer to the hwAttrs */
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hwAttrs = (UDMACC26XX_HWAttrs *)(handle->hwAttrs);
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/* Enable DMA channel */
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HWREG(hwAttrs->baseAddr + UDMA_O_SETCHANNELEN) = channelBitMask;
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}
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/*!
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* @internal
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* @brief Function to see if a given DMA channel is done.
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*
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* Will read the request done signal for the give channels
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* and return true if all channels are done, otherwise false.
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*
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* @pre UDMACC26XX_open() has to be called first.
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* Calling context: Hwi, Swi, Task
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*
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* @param handle A SPI_Handle returned from SPI_open()
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*
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* @param params A 32-bit bitmask of the channels to check for if are done.
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*
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* @return True if the channels are done, false otherwise.
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*
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* @sa SPICC26XXDMA_open, UDMACC26XX_channelDisable
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*/
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__STATIC_INLINE bool UDMACC26XX_channelDone(UDMACC26XX_Handle handle, uint32_t channelBitMask)
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{
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UDMACC26XX_HWAttrs const *hwAttrs;
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/* Get the pointer to the hwAttrs */
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hwAttrs = (UDMACC26XX_HWAttrs *)(handle->hwAttrs);
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/* Check if REQDONE is set for a specific channel */
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return (uDMAIntStatus(hwAttrs->baseAddr) & channelBitMask) ? true : false;
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}
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/*!
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* @internal
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* @brief Function to clear a given DMA channel interrupt.
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*
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* Will clear the DMA interrupt(s) for the given bitmask provided.
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*
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* @pre UDMACC26XX_open() has to be called first.
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* Calling context: Hwi, Swi, Task
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*
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* @param handle A SPI_Handle returned from SPI_open()
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*
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* @param params A 32-bit bitmask of the channels to check for if are done.
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*
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* @param channelBitMask A 32-bit bitmask of the channels to clear interrupts for.
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*
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* @return none
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*/
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__STATIC_INLINE void UDMACC26XX_clearInterrupt(UDMACC26XX_Handle handle, uint32_t channelBitMask)
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{
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UDMACC26XX_HWAttrs const *hwAttrs;
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/* Get the pointer to the hwAttrs and object */
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hwAttrs = (UDMACC26XX_HWAttrs *)(handle->hwAttrs);
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/* Clear UDMA done interrupt */
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uDMAIntClear(hwAttrs->baseAddr, channelBitMask);
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}
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/*!
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* @internal
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* @brief Function to disable one or more DMA channels.
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*
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* Will disable the channel(s) for the given bitmask provided.
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*
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* @pre UDMACC26XX_open() has to be called first.
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* Calling context: Hwi, Swi, Task
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*
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* @param handle A SPI_Handle returned from SPI_open()
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*
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* @param params A 32-bit bitmask of the channels to disable.
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*
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* @return none
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*
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* @sa UDMACC26XX_channelEnable
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*/
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__STATIC_INLINE void UDMACC26XX_channelDisable(UDMACC26XX_Handle handle, uint32_t channelBitMask)
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{
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UDMACC26XX_HWAttrs const *hwAttrs = handle->hwAttrs;
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HWREG(hwAttrs->baseAddr + UDMA_O_CLEARCHANNELEN) = channelBitMask;
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}
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/*!
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* @internal
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* @brief Function to disable a DMA channel's attributes.
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*
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* Will disable a channel's attributes.
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*
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* @pre UDMACC26XX_open() has to be called first.
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* Calling context: Hwi, Swi, Task
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*
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* @param handle A UDMACC26XX_Handle returned from UDMACC26XX_open()
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*
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* @param channelNum the channel to configure.
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*
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* @param attr Channel attribute to disable.
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*
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*
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* @return none
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*
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* @sa UDMACC26XX_channelEnable
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*/
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__STATIC_INLINE void UDMACC26XX_disableAttribute(UDMACC26XX_Handle handle,
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uint32_t channelNum, uint32_t attr)
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{
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UDMACC26XX_HWAttrs const *hwAttrs = (UDMACC26XX_HWAttrs *) handle->hwAttrs;
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uDMAChannelAttributeDisable(hwAttrs->baseAddr, channelNum, attr);
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}
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/*!
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* @brief Function to close the DMA driver.
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*
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* Will disable the DMA hardware, release the power dependency and destruct
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* the HWI interrupt.
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*
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* @pre UDMACC26XX_open() has to be called first.
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* Calling context: Task
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*
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* @param handle A SPI_Handle returned from SPI_open()
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*
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* @return none
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*
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* @sa SPICC26XXDMA_open
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*/
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extern void UDMACC26XX_close(UDMACC26XX_Handle handle);
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#ifdef __cplusplus
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}
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#endif
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#endif /* ti_drivers_UDMACC26XX__include */
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